On Tue, Jun 6, 2017 at 3:18 PM, Mika Westerberg <[email protected]> wrote:
> The Intel GPIO hardware has a concept of pad groups, which means 1 to 32 > pads occupying their own GPI_IS, GPI_IE, PAD_OWN and so on registers. The > existing hardware has the same amount of pads in each pad group (except the > last one) so it is possible to use community->gpp_size to calculate start > offset of each register. > > With the next generation SoCs the pad group size is not always the same > anymore which means we cannot use community->gpp_size for register offset > calculations directly. > > To support variable size pad groups we introduce struct intel_padgroup that > can be filled in by the client drivers according the hardware pad group > layout. The core driver will always use these when it performs calculations > for pad register offsets. The core driver will automatically populate pad > groups based on community->gpp_size if the driver does not provide any. > This makes sure the existing drivers still work as expected. > > Signed-off-by: Mika Westerberg <[email protected]> > Signed-off-by: Chuah, Kim Tatt <[email protected]> > Signed-off-by: Tan Jui Nee <[email protected]> > Reviewed-by: Andy Shevchenko <[email protected]> Patch applied! Yours, Linus Walleij
