Ram Pai <linux...@us.ibm.com> writes:

> Replace the magic number used to check for DSI exception
> with a meaningful value.
>
> Signed-off-by: Ram Pai <linux...@us.ibm.com>
> ---
>  arch/powerpc/include/asm/reg.h       | 9 ++++++++-
>  arch/powerpc/kernel/exceptions-64s.S | 2 +-
>  2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
> index 7e50e47..2dcb8a1 100644
> --- a/arch/powerpc/include/asm/reg.h
> +++ b/arch/powerpc/include/asm/reg.h
> @@ -272,16 +272,23 @@
>  #define SPRN_DAR     0x013   /* Data Address Register */
>  #define SPRN_DBCR    0x136   /* e300 Data Breakpoint Control Reg */
>  #define SPRN_DSISR   0x012   /* Data Storage Interrupt Status Register */
> +#define   DSISR_BIT32                0x80000000      /* not defined */
>  #define   DSISR_NOHPTE               0x40000000      /* no translation found 
> */
> +#define   DSISR_PAGEATTR_CONFLT      0x20000000      /* page attribute 
> conflict */
> +#define   DSISR_BIT35                0x10000000      /* not defined */
>  #define   DSISR_PROTFAULT    0x08000000      /* protection fault */
>  #define   DSISR_BADACCESS    0x04000000      /* bad access to CI or G */
>  #define   DSISR_ISSTORE              0x02000000      /* access was a store */
>  #define   DSISR_DABRMATCH    0x00400000      /* hit data breakpoint */
> -#define   DSISR_NOSEGMENT    0x00200000      /* SLB miss */
>  #define   DSISR_KEYFAULT     0x00200000      /* Key fault */
> +#define   DSISR_BIT43                0x00100000      /* not defined */
>  #define   DSISR_UNSUPP_MMU   0x00080000      /* Unsupported MMU config */
>  #define   DSISR_SET_RC               0x00040000      /* Failed setting of 
> R/C bits */
>  #define   DSISR_PGDIRFAULT      0x00020000      /* Fault on page directory */
> +#define   DSISR_PAGE_FAULT_MASK (DSISR_BIT32 | \
> +                             DSISR_PAGEATTR_CONFLT | \
> +                             DSISR_BADACCESS |       \
> +                             DSISR_BIT43)
>  #define SPRN_TBRL    0x10C   /* Time Base Read Lower Register (user, R/O) */
>  #define SPRN_TBRU    0x10D   /* Time Base Read Upper Register (user, R/O) */
>  #define SPRN_CIR     0x11B   /* Chip Information Register (hyper, R/0) */
> diff --git a/arch/powerpc/kernel/exceptions-64s.S 
> b/arch/powerpc/kernel/exceptions-64s.S
> index ae418b8..3fd0528 100644
> --- a/arch/powerpc/kernel/exceptions-64s.S
> +++ b/arch/powerpc/kernel/exceptions-64s.S
> @@ -1411,7 +1411,7 @@ USE_TEXT_SECTION()
>       .balign IFETCH_ALIGN_BYTES
>  do_hash_page:
>  #ifdef CONFIG_PPC_STD_MMU_64
> -     andis.  r0,r4,0xa410            /* weird error? */
> +     andis.  r0,r4,DSISR_PAGE_FAULT_MASK@h
>       bne-    handle_page_fault       /* if not, try to insert a HPTE */
>       andis.  r0,r4,DSISR_DABRMATCH@h
>       bne-    handle_dabr_fault


Thanks for doing this. I always wondered what that 0xa410 indicates. Now
tha it is documented, I am wondering are those the only DSISR values
that we want to check early ? You also added few bit positions that is
expected to carry value 0 ? But then excluded BIT35. Any reason ?

-aneesh

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