On Wed, Jul 26, 2017 at 01:53:28PM +0200, Peter Zijlstra wrote: > > New version.. > > > --- > Subject: documentation,atomic: Add new documents > From: Peter Zijlstra <[email protected]> > Date: Mon Jun 12 14:50:27 CEST 2017 > > Since we've vastly expanded the atomic_t interface in recent years the > existing documentation is woefully out of date and people seem to get > confused a bit. > > Start a new document to hopefully better explain the current state of > affairs. > > The old atomic_ops.txt also covers bitmaps and a few more details so > this is not a full replacement and we'll therefore keep that document > around until such a time that we've managed to write more text to cover > its entire. >
You seems have a unfinished paragraph.. > Also please, ReST people, go away. > > Signed-off-by: Peter Zijlstra (Intel) <[email protected]> > --- [...] > + > +Further, while something like: > + > + smp_mb__before_atomic(); > + atomic_dec(&X); > + > +is a 'typical' RELEASE pattern, the barrier is strictly stronger than > +a RELEASE. Similarly for something like: > + .. at here. Maybe you planned to put stronger ACQUIRE pattern? > + > --- a/Documentation/memory-barriers.txt > +++ b/Documentation/memory-barriers.txt > @@ -498,7 +498,7 @@ VARIETIES OF MEMORY BARRIER > This means that ACQUIRE acts as a minimal "acquire" operation and > RELEASE acts as a minimal "release" operation. > [...] > - > -[!] Note that special memory barrier primitives are available for these > -situations because on some CPUs the atomic instructions used imply full > memory > -barriers, and so barrier instructions are superfluous in conjunction with > them, > -and in such cases the special barrier primitives will be no-ops. > - > -See Documentation/core-api/atomic_ops.rst for more information. > +See Documentation/atomic_t.txt for more information. > s/atomic_t.txt/atomic_{t,bitops}.txt/ ? other than those two tiny things, Reviewed-by: Boqun Feng <[email protected]> Regards, Boqun > > ACCESSING DEVICES
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