This patch prepare decompression code to boot-time switching between 4-
and 5-level paging.

Signed-off-by: Kirill A. Shutemov <kirill.shute...@linux.intel.com>
---
 arch/x86/boot/compressed/head_64.S | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/x86/boot/compressed/head_64.S 
b/arch/x86/boot/compressed/head_64.S
index fbf4c32d0b62..2e362aea3319 100644
--- a/arch/x86/boot/compressed/head_64.S
+++ b/arch/x86/boot/compressed/head_64.S
@@ -347,6 +347,28 @@ preferred_addr:
        leaq    boot_stack_end(%rbx), %rsp
 
 #ifdef CONFIG_X86_5LEVEL
+       /* Preserve rbx across cpuid */
+       movq    %rbx, %r8
+
+       /* Check if leaf 7 is supported */
+       movl    $0, %eax
+       cpuid
+       cmpl    $7, %eax
+       jb      lvl5
+
+       /*
+        * Check if la57 is supported.
+        * The feature is enumerated with CPUID.(EAX=07H, ECX=0):ECX[bit 16]
+        */
+       movl    $7, %eax
+       movl    $0, %ecx
+       cpuid
+       andl    $(1 << 16), %ecx
+       jz      lvl5
+
+       /* Restore rbx */
+       movq    %r8, %rbx
+
        /* Check if 5-level paging has already enabled */
        movq    %cr4, %rax
        testl   $X86_CR4_LA57, %eax
@@ -386,6 +408,8 @@ preferred_addr:
        pushq   %rax
        lretq
 lvl5:
+       /* Restore rbx */
+       movq    %r8, %rbx
 #endif
 
        /* Zero EFLAGS */
-- 
2.13.2

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