Le Sat,  5 Aug 2017 21:49:39 +0530,
Abhishek Sahu <abs...@codeaurora.org> a écrit :

> The NAND page read fails without complete boot chain since
> NAND_DEV_CMD_VLD value is not proper. The default power on reset
> value for this register is
> 
>     0xe - ERASE_START_VALID | WRITE_START_VALID | READ_STOP_VALID
> 
> The READ_START_VALID should be enabled for sending PAGE_READ
> command. READ_STOP_VALID should be cleared since normal NAND
> page read does not require READ_STOP command.
> 
> Fixes: c76b78d8ec05a ("mtd: nand: Qualcomm NAND controller driver")
> Cc: sta...@vger.kernel.org
> Reviewed-by: Archit Taneja <arch...@codeaurora.org>
> Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
> ---
>  drivers/mtd/nand/qcom_nandc.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 0289f09..7406019 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -110,6 +110,10 @@
>  
>  /* NAND_DEV_CMD_VLD bits */
>  #define      READ_START_VLD                  0
> +#define      READ_STOP_VALID                 1
> +#define      WRITE_START_VALID               2
> +#define      ERASE_START_VALID               3
> +#define      SEQ_READ_START_VLD              4

Why not

#define READ_START_VLD                          BIT(0)
#define READ_STOP_VALID                         BIT(1)
#define WRITE_START_VALID                       BIT(2)
#define ERASE_START_VALID                       BIT(3)
#define SEQ_READ_START_VLD                      BIT(4)

>  
>  /* NAND_EBI2_ECC_BUF_CFG bits */
>  #define      NUM_STEPS                       0
> @@ -148,6 +152,12 @@
>  #define      FETCH_ID                        0xb
>  #define      RESET_DEVICE                    0xd
>  
> +/* Default Value for NAND_DEV_CMD_VLD */
> +#define NAND_DEV_CMD_VLD_VAL         (BIT(READ_START_VLD)    | \
> +                                      BIT(WRITE_START_VALID) | \
> +                                      BIT(ERASE_START_VALID) | \
> +                                      BIT(SEQ_READ_START_VLD))
> +

and then:

#define NAND_DEV_CMD_VLD_VAL    (READ_START_VLD | \
                                 WRITE_START_VALID | \
                                 ERASE_START_VALID | \
                                 SEQ_READ_START_VLD)

BTW, can you use consistent suffixes? Sometime definitions are suffixed
with _VLD and others are suffixed with _VALID.

>  /*
>   * the NAND controller performs reads/writes with ECC in 516 byte chunks.
>   * the driver calls the chunks 'step' or 'codeword' interchangeably
> @@ -1995,13 +2005,14 @@ static int qcom_nandc_setup(struct 
> qcom_nand_controller *nandc)
>  {
>       /* kill onenand */
>       nandc_write(nandc, SFLASHC_BURST_CFG, 0);
> +     nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);
>  
>       /* enable ADM DMA */
>       nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
>  
>       /* save the original values of these registers */
>       nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1);
> -     nandc->vld = nandc_read(nandc, NAND_DEV_CMD_VLD);
> +     nandc->vld = NAND_DEV_CMD_VLD_VAL;
>  
>       return 0;
>  }

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