在 2017-08-12 20:43,Icenowy Zheng 写道:
From: Priit Laes <pl...@plaes.org>

SATA clock on sun4i/sun7i is of type (parent) / M / 6 where
6 is fixed post-divider.

Signed-off-by: Priit Laes <pl...@plaes.org>

Signed-off-by: Icenowy Zheng <icen...@aosc.io>

---
It's based on the patch in v6 of the A10/A20 CCU patchset, but with
ccu_div_round_rate fixed.

 drivers/clk/sunxi-ng/ccu_div.c | 22 +++++++++++++++++++---
 drivers/clk/sunxi-ng/ccu_div.h |  3 ++-
 2 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_div.c
index c0e5c10d0091..baa3cf96507b 100644
--- a/drivers/clk/sunxi-ng/ccu_div.c
+++ b/drivers/clk/sunxi-ng/ccu_div.c
@@ -21,10 +21,18 @@ static unsigned long ccu_div_round_rate(struct
ccu_mux_internal *mux,
 {
        struct ccu_div *cd = data;

-       return divider_round_rate_parent(&cd->common.hw, parent,
+       if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
+               rate *= cd->fixed_post_div;
+
+       rate = divider_round_rate_parent(&cd->common.hw, parent,
                                         rate, parent_rate,
                                         cd->div.table, cd->div.width,
                                         cd->div.flags);
+
+       if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
+               rate /= cd->fixed_post_div;
+
+       return rate;
 }

 static void ccu_div_disable(struct clk_hw *hw)
@@ -62,8 +70,13 @@ static unsigned long ccu_div_recalc_rate(struct clk_hw *hw,
        parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1,
                                                  parent_rate);

-       return divider_recalc_rate(hw, parent_rate, val, cd->div.table,
-                                  cd->div.flags);
+       val = divider_recalc_rate(hw, parent_rate, val, cd->div.table,
+                                 cd->div.flags);
+
+       if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
+               val /= cd->fixed_post_div;
+
+       return val;
 }

 static int ccu_div_determine_rate(struct clk_hw *hw,
@@ -86,6 +99,9 @@ static int ccu_div_set_rate(struct clk_hw *hw,
unsigned long rate,
        parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1,
                                                  parent_rate);

+       if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
+               rate *= cd->fixed_post_div;
+
val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width,
                              cd->div.flags);

diff --git a/drivers/clk/sunxi-ng/ccu_div.h b/drivers/clk/sunxi-ng/ccu_div.h
index 08d074451204..f3a5028dcd14 100644
--- a/drivers/clk/sunxi-ng/ccu_div.h
+++ b/drivers/clk/sunxi-ng/ccu_div.h
@@ -86,9 +86,10 @@ struct ccu_div_internal {
 struct ccu_div {
        u32                     enable;

-       struct ccu_div_internal         div;
+       struct ccu_div_internal div;
        struct ccu_mux_internal mux;
        struct ccu_common       common;
+       unsigned int            fixed_post_div;
 };

 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg,   \

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