On Mon, Oct 30 2017 at 8:11:15 am GMT, Stafford Horne <sho...@gmail.com> wrote:
> From: Stefan Kristiansson <stefan.kristians...@saunalahti.fi>
>
> IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as
> described in the Multi-core support section of the OpenRISC 1.2
> architecture specification:
>
> https://github.com/openrisc/doc/raw/master/openrisc-arch-1.2-rev0.pdf
>
> Each OpenRISC core contains a full interrupt controller which is used in
> the SMP architecture for interrupt balancing. This IPI device, the
> ompic, is the only external device required for enabling SMP on
> OpenRISC.
>
> Pending ops are stored in a memory bit mask which can allow multiple
> pending operations to be set and serviced at a time. This is mostly
> borrowed from the alpha IPI implementation.
>
> Cc: Marc Zyngier <marc.zyng...@arm.com>
> Acked-by: Rob Herring <r...@kernel.org>
> Signed-off-by: Stefan Kristiansson <stefan.kristians...@saunalahti.fi>
> [sho...@gmail.com: converted ops to bitmask, wrote commit message]
> Signed-off-by: Stafford Horne <sho...@gmail.com>
Reviewed-by: Marc Zyngier <marc.zyng...@arm.com>
Side question: what is your merge strategy for this? I can take it
through the irqchip tree as it is standalone, but I'm open to other
suggestions.
Thanks,
M.
--
Jazz is not dead. It just smells funny.
