On Wed, Nov 08, 2017 at 11:46:49AM -0800, Dave Hansen wrote: > > From: Dave Hansen <[email protected]> > > Our CR4-based TLB flush currently requries global pages to be > supported *and* enabled. But, the hardware only needs for them to > be supported. > > Make the code more robust by alllowing the initial state of > X86_CR4_PGE to be on *or* off. In addition, if we get called in > an unepected state (X86_CR4_PGE=0), issue a warning. Having > X86_CR4_PGE=0 is certainly unexpected and we should not ignore > it if encountered. > > This essentially gives us the best of both worlds: we get a TLB > flush no matter what, and we get a warning if we got called in > an unexpected way (X86_CR4_PGE=0).
Commit message could use a spell checker. > The XOR change was suggested by Kirill Shutemov. > > Signed-off-by: Dave Hansen <[email protected]> > Cc: Moritz Lipp <[email protected]> > Cc: Daniel Gruss <[email protected]> > Cc: Michael Schwarz <[email protected]> > Cc: Richard Fellner <[email protected]> > Cc: Andy Lutomirski <[email protected]> > Cc: Linus Torvalds <[email protected]> > Cc: Kees Cook <[email protected]> > Cc: Hugh Dickins <[email protected]> > Cc: [email protected] > --- > > b/arch/x86/include/asm/tlbflush.h | 17 ++++++++++++++--- > 1 file changed, 14 insertions(+), 3 deletions(-) > > diff -puN > arch/x86/include/asm/tlbflush.h~kaiser-prep-make-cr4-writes-tolerate-clear-pge > arch/x86/include/asm/tlbflush.h > --- > a/arch/x86/include/asm/tlbflush.h~kaiser-prep-make-cr4-writes-tolerate-clear-pge > 2017-11-08 10:45:26.461681402 -0800 > +++ b/arch/x86/include/asm/tlbflush.h 2017-11-08 10:45:26.464681402 -0800 > @@ -250,9 +250,20 @@ static inline void __native_flush_tlb_gl > unsigned long cr4; > > cr4 = this_cpu_read(cpu_tlbstate.cr4); > - /* clear PGE */ > - native_write_cr4(cr4 & ~X86_CR4_PGE); > - /* write old PGE again and flush TLBs */ <---- newline here. > + /* > + * This function is only called on systems that support X86_CR4_PGE > + * and where always set X86_CR4_PGE. Warn if we are called without "... and where X86_CR4_PGE is normally always set." > + * PGE set. > + */ > + WARN_ON_ONCE(!(cr4 & X86_CR4_PGE)); <---- newline here. > + /* > + * Architecturally, any _change_ to X86_CR4_PGE will fully flush the > + * TLB of all entries including all entries in all PCIDs and all > + * global pages. Make sure that we _change_ the bit, regardless of > + * whether we had X86_CR4_PGE set in the first place. ... or not." > + */ > + native_write_cr4(cr4 ^ X86_CR4_PGE); <---- newline here. > + /* Put original CR4 value back: */ > native_write_cr4(cr4); > } Btw, Andy, we read the CR4 shadow in that function but we don't update it. Why? -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.
