Add binding documentation for the Microsemi Ocelot reset block.
Signed-off-by: Alexandre Belloni <[email protected]>
---
Cc: Rob Herring <[email protected]>
Cc: [email protected]
To: Sebastian Reichel <[email protected]>
Cc: [email protected]
.../bindings/power/reset/ocelot-reset.txt | 24 ++++++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644
Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
new file mode 100644
index 000000000000..2d3f2c21fadd
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
@@ -0,0 +1,24 @@
+Microsemi Ocelot reset driver
+
+The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
+SoC MIPS core.
+
+Required Properties:
+ - compatible: "mscc,ocelot-chip-reset"
+ - mscc,cpucontrol: phandle to the CPU system control syscon block
+
+Example:
+ cpu_ctrl: syscon@70000000 {
+ compatible = "syscon";
+ reg = <0x70000000 0x2c>;
+ };
+
+ syscon@71070000 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x71070000 0x1c>;
+
+ reset {
+ compatible = "mscc,ocelot-chip-reset";
+ mscc,cpucontrol = <&cpu_ctrl>;
+ };
+ };
--
2.15.0
