On 20/12/2017 20:40, Jim Mattson wrote: > This doesn't look right to me. Without APIC-register virtualization, > the only X2APIC MSR intercept that should be disabled is TPR.
Of course... The bitmap that has to be outside the "if" is *_x2apic_apicv, not *_x2apic. I sent the wrong version of the series (and this was the only difference, together s/superset/subset/ in the commit message). Will resend tomorrow. Paolo > On Wed, Dec 20, 2017 at 4:05 AM, Paolo Bonzini <[email protected]> wrote: >> The APICv-enabled MSR bitmap is a superset of the APICv-disabled bitmap. >> Make that obvious in vmx_disable_intercept_msr_x2apic. >> >> Signed-off-by: Paolo Bonzini <[email protected]> >> --- >> arch/x86/kvm/vmx.c | 8 ++------ >> 1 file changed, 2 insertions(+), 6 deletions(-) >> >> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c >> index 9f9c3194440f..905aaa778306 100644 >> --- a/arch/x86/kvm/vmx.c >> +++ b/arch/x86/kvm/vmx.c >> @@ -5263,12 +5263,9 @@ static void vmx_disable_intercept_msr_x2apic(u32 msr, >> int type, bool apicv_activ >> msr, type); >> >> __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv, >> msr, type); >> - } else { >> - __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic, >> - msr, type); >> - >> __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic, >> - msr, type); >> } >> + __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic, msr, >> type); >> + __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic, msr, >> type); >> } >> >> static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu) >> @@ -7148,7 +7145,6 @@ static __init int hardware_setup(void) >> * TPR reads and writes can be virtualized even if virtual interrupt >> * delivery is not in use. >> */ >> - vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true); >> vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, >> false); >> >> /* EOI */ >> -- >> 1.8.3.1 >> >>
