On 10/01/2018 21:13, Tom Lendacky wrote: > On 1/9/2018 6:03 AM, Paolo Bonzini wrote: >> Direct access to MSR_IA32_SPEC_CTRL and MSR_IA32_PRED_CMD is important >> for performance. Allow load/store of MSR_IA32_SPEC_CTRL, restore guest >> IBRS on VM entry and set it to 0 on VM exit (because Linux does not use >> it yet). >> >> Signed-off-by: Paolo Bonzini <[email protected]> >> --- >> arch/x86/kvm/svm.c | 42 ++++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 42 insertions(+) >> >> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c >> index 31ace8d7774a..934a21e02e03 100644 >> --- a/arch/x86/kvm/svm.c >> +++ b/arch/x86/kvm/svm.c > > ... > >> @@ -5015,6 +5045,18 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu) >> #endif >> ); >> >> + if (have_spec_ctrl) { >> + rdmsrl(MSR_IA32_SPEC_CTRL, svm->spec_ctrl); >> + if (svm->spec_ctrl != 0) >> + wrmsrl(MSR_IA32_SPEC_CTRL, 0); >> + } >> + /* >> + * Speculative execution past the above wrmsrl might encounter >> + * an indirect branch and use guest-controlled contents of the >> + * indirect branch predictor; block it. >> + */ >> + asm("lfence"); > > This will end up needing to be an alternative macro based on the > LFENCE_RDTSC or MFENCE_RDTSC features [1]. You'll probably just want to > use the speculation barrier macro that ends up being defined to control > the speculation here.
Yes. Though, is there any processor that has spec_ctrl (which is none on AMD) but needs a full fence? Paolo > Thanks, > Tom > > [1] https://marc.info/?l=linux-kernel&m=151545930207815&w=2 > >> + >> #ifdef CONFIG_X86_64 >> wrmsrl(MSR_GS_BASE, svm->host.gs_base); >> #else >>
