Il 02/02/2018 11:53, Maxime Ripard ha scritto:
On Thu, Feb 01, 2018 at 05:17:11PM +0100, Giulio Benetti wrote:
What kernel version did you use?
I guess this patch could fix it:
This should prevent from modifying parent clock. But my problem was
On A20, gpu_clk can have different PLL, not I've found out the way
to choose right one with assigned-parent-clocks.
I have patchset ready for adding A20 mali node, but I need some more
time to complete with OPP, then I will submit entire patchset.
Now it works correctly, using right pll(dedicated PLL8), setting
The point is that we really don't care about which PLL is actually
being used, as long as the rate is correct and we don't break anything
else. If the GPU rate is accessible through one of the other PLL, it
makes even more sense to not use the GPU PLL and keep it disabled,
since it will result in some power savings.
Ah! I see the point now, very clever system for power saving.
I'm going to check if it's resolutive,
but it sounds good.
Btw, do I need to add a board using it, or can I add only Mali node
to sun7i-a20.dtsi(plus other little patches)?
You can add it to the DTSI without a board using it (and actually,
nothing should be in the board DTS, everything in the DT for the Mali
applies to all boards).
Sure. So I would also add the patch you've addressed me:
as a commit. Can I submit it in patchset to complete the whole job?
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