On Fri, Feb 02 2018 at 16:28 +0000, Marc Zyngier wrote:
On 02/02/18 14:21, Lina Iyer wrote:
From: Archana Sathyakumar <asath...@codeaurora.org>

Add device binding documentation for the PDC Interrupt controller on
QCOM SoC's like the SDM845. The interrupt-controller can be used to
sense edge low interrupts and wakeup interrupts when the GIC is

Cc: devicet...@vger.kernel.org
Signed-off-by: Archana Sathyakumar <asath...@codeaurora.org>
Signed-off-by: Lina Iyer <il...@codeaurora.org>
 .../bindings/interrupt-controller/qcom,pdc.txt     | 78 ++++++++++++++++++++++
 1 file changed, 78 insertions(+)
 create mode 100644 

diff --git 
new file mode 100644
index 000000000000..7bf40cb6a4f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
@@ -0,0 +1,78 @@
+PDC interrupt controller
+Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
+Power Domain Controller (PDC) that is on always-on domain. In addition to
+providing power control for the power domains, the hardware also has an
+interrupt controller that can be used to help detect edge low interrupts as
+well detect interrupts when the GIC is non-operational.
+GIC is parent interrupt controller at the highest level. Platform interrupt
+controller PDC is next in hierarchy, followed by others. Drivers requiring
+wakeup capabilities of their device interrupts routed through the PDC, must
+specify PDC as their interrupt controller and request the PDC port associated
+with the GIC interrupt. See example below.
+- compatible:
+       Usage: required
+       Value type: <string>
+       Definition: Should contain "qcom,<soc>-pdc"
+                   - "qcom,sdm845-pdc": For SDM845
+- reg:
+       Usage: required
+       Value type: <prop-encoded-array>
+       Definition: Specifies the base physical address for PDC hardware.
+- interrupt-cells:
+       Usage: required
+       Value type: <u32>
+       Definition: Specifies the number of cells needed to encode an interrupt
+                   source.
+                   The value must match that of the parent interrupt
+                   controller defined in the DT.
+                   The encoding of these cells are same as described in [1].

There shouldn't be such a requirement. These are two independent pieces
of HW, and the first parameter doesn't mean anything for the PDC.

Wouldn't that be confusing - that we have different definitions for
interrupts in the same DT? I agree that they are different interrupt
controllers, but it just feels odd.

I will change this to just take 2 cells.

+- interrupt-parent:
+       Usage: required
+       Value type: <phandle>
+       Definition: Specifies the interrupt parent necessary for hierarchical
+                   domain to operate.
+- interrupt-controller:
+       Usage: required
+       Value type: <bool>
+       Definition: Identifies the node as an interrupt controller.
+- qcom,pdc-range:
+       Usage: required
+       Value type: <u32 array>
+       Definition: Specifies the PDC pin offset and the number of PDC ports.
+                   The tuples indicates the valid mapping of valid PDC ports
+                   and their hwirq mapping.
+                   The first element of the tuple is the staring PDC port num.
+                   The second element is the hwirq number for the PDC port.
+                   The third element is the number of elements in sequence.
+       pdc: interrupt-controller@b220000 {
+               compatible = "qcom,sdm845-pdc";
+               reg = <0xb220000 0x30000>;
+               qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
+               #interrupt-cells = <3>;
+               interrupt-parent = <&intc>;
+               interrupt-controller;
+       };
+The DT binding of a device that wants to use the GIC SPI 514 as a wakeup
+interrupt, would look like this -
+       wake-device {
+               [...]
+               interrupt-parent = <&pdc>;
+               interrupt = <0 2 0>;

Again: 0 is not a valid trigger value.



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