On 02/02/2018 08:20 AM, Sekhar Nori wrote:
On Saturday 20 January 2018 10:44 PM, David Lechner wrote:
  void __init da850_init_time(void)
  {
+#ifdef CONFIG_COMMON_CLK
+       void __iomem *pll0, *pll1, *psc0, *psc1;
+       struct regmap *cfgchip;
+       struct clk *clk;
+       struct clk_hw *parent;
+
+       pll0 = ioremap(DA8XX_PLL0_BASE, SZ_4K);
+       pll1 = ioremap(DA850_PLL1_BASE, SZ_4K);
+       psc0 = ioremap(DA8XX_PSC0_BASE, SZ_4K);
+       psc1 = ioremap(DA8XX_PSC1_BASE, SZ_4K);
+
+       cfgchip = da8xx_register_cfgchip();
+       if (WARN(IS_ERR(cfgchip), "failed to register CFGCHIP syscon"))
+               return;
+
+       clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ);
+
+       da850_pll_clk_init(pll0, pll1);
+
+       da8xx_cfgchip_register_div4p5(cfgchip);
+
+       da8xx_cfgchip_register_async1(cfgchip);
+
+       clk = clk_register_fixed_factor(NULL, "async2", "pll0_auxclk", 0, 1, 1);
+       clk_register_clkdev(clk, NULL, "i2c_davinci.1");
+       clk_register_clkdev(clk, "timer0", NULL);
+       clk_register_clkdev(clk, NULL, "davinci-wdt");


I think its better to get these clkdevs registered in
da850_pll_clk_init() itself.

Sounds good to me.


+
+       clk = da8xx_cfgchip_register_async3(cfgchip);
+
+       /* pll1_sysclk2 is not affected by CPU scaling, so use it for async3 */
+       parent = clk_hw_get_parent_by_index(__clk_get_hw(clk), 1);
+       if (parent)
+               clk_set_parent(clk, parent->clk);
+       else
+               pr_warn("%s: Failed to find async3 parent clock\n", __func__);
+
+       da850_psc_clk_init(psc0, psc1);
+
+       clk = clk_register_fixed_factor(NULL, "rmii", "pll0_sysclk7", 0, 1, 1);
+       clk_register_clkdev(clk, "rmii", NULL);

Like in da830, can drop this rmii clock, I think.

Thanks,
Sekhar


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