On Wed, Feb 07, 2018 at 10:51:55AM +0000, Suzuki K Poulose wrote: > On 07/02/18 10:43, Dave Martin wrote: > >On Thu, Feb 01, 2018 at 10:38:38AM +0000, Suzuki K Poulose wrote: > >>Expose the new features introduced by Arm v8.4 extensions to > >>Arm v8-A profile. > >> > >>These include : > >> > >> 1) Data indpendent timing of instructions. (DIT, exposed as HWCAP_DIT) > >> 2) Unaligned atomic instructions and Single-copy atomicity of loads > >> and stores. (AT, expose as HWCAP_USCAT) > >> 3) LDAPR and STLR instructions with immediate offsets (extension to > >> LRCPC, exposed as HWCAP_ILRCPC) > >> 4) Flag manipulation instructions (TS, exposed as HWCAP_FLAGM). > >> > >>While at it get rid of the RES0 entries in the cpu-feature-registers.txt > >>documentation. > > > >Should we write somewhere than fields that are not described here are > >implicitly RES0, or would that be too strong a statement? > > Dave, > > We already have the following description in the file : > > "The following rules are applied to the value returned by the > infrastructure: > > a) The value of an 'IMPLEMENTATION DEFINED' field is set to 0. > b) The value of a reserved field is populated with the reserved > value as defined by the architecture. > c) The value of a 'visible' field holds the system wide safe value > for the particular feature (except for MIDR_EL1, see section 4). > d) All other fields (i.e, invisible fields) are set to indicate > the feature is missing (as defined by the architecture). > " > > So we don't have to bother if the fields are RES0 or they get > some definitions in the future, as long as we don't expose them.
Agreed, that does seem sufficient: Reviewed-by: Dave Martin <[email protected]> [...] Cheers ---Dave
