On Tue, Feb 13, 2018 at 9:25 AM, Philipp Rossak <embe...@gmail.com> wrote:
> On 12.02.2018 19:21, Philipp Rossak wrote:
>> When I try to boot my A31s (Bananapi M2) u-boot is showing only Starting
>> kernel ... . After enabling the earlyprintk I could capture this log: .
>> After reverting those 5 commits from Chen-Yu I was able to boot again:
>> clk: sunxi-ng: Support fixed post-dividers on NM style clocks
>> clk: sunxi-ng: sun8i: a83t: Add /2 fixed post divider to audio PLL
>> clk: sunxi-ng: sun8i: a83t: Use sigma-delta modulation for audio PLL
>> clk: sunxi-ng: Support fixed post-dividers on MP style clocks
>> clk: sunxi-ng: sun50i: a64: Add 2x fixed post-divider to MMC module clocks
>> I allready tried to fix it with making them save against zero:
>> if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV && \
>> cmp->fixed_post_div with)
>> rate *= cmp->fixed_post_div;
>> But that didn't help.
>> Any ideas?
>> : https://pastebin.com/64Fzzqvg
> It took me some time, but I have now a few more infos:
> Right now the code breaks at this point here , with this clock .
> If we have a look now at the clock config , we see here a table which is
> an u8 array and also a fixed_predivs struct.
The u8 array is for mapping the parents from the index in the parents
array to the actual register value you listed below.
How are you figuring out which clock is triggering this? Because that
is not even the right type of clock. The backtrace you posted shows
the error occurring in a DIV or M type clock, not the MP type you
are pointing to.
Could you add some noisy printk calls to the sunxi_ccu_probe()
function in drivers/clk/sunxi-ng/ccu_common.c so it's much clearer
which clock is failing?
> If we have a look at the function call where it breaks , shouldn't the
> table be a clk_div_table struct instead of an u8?
The table argument is an option. Did you go through how the sunxi-ng driver
calls this function? As mentioned above, you are looking at the wrong thing.
> The a31s is the only board where we have this combination of a fixed_predivs
> and a table.
> Related Clock source register A31s:
> 0000: OSC24MHz/750=32KHz
> 0001: LOSC
> 0010: OSC24MHz
> 0011: /
> 0100: /
> 0101: /
> 0110: /
> 0111: /
> 1000: /
> 1001: /
> 1010: /
> 1011: AXICLK/4
> 1100: /
> 1101: AHB1CLK/4
> 1110: /
> 1111: /