Re: [v2,7/8] clk: divider: read-only divider can propagate rate change

[David Lechner]

On 02/14/2018 07:43 AM, Jerome Brunet wrote:

When a divider clock has CLK_DIVIDER_READ_ONLY set, it means that the
register shall be left un-touched, but it does not mean the clock
should stop rate propagation if CLK_SET_RATE_PARENT is set

This is properly handled in qcom clk-regmap-divider but it was not in
the generic divider

To fix this situation, introduce a new helper function
divider_ro_round_rate, on the same model as divider_round_rate.

Fixes: e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1")
Signed-off-by: Jerome Brunet <jbru...@baylibre.com>
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Working for me with the davinci clk drivers I am developing.

Tested-By: David Lechner <da...@lechnology.com>