4.4-stable review patch.  If anyone has any objections, please let me know.


From: Dan Williams <dan.j.willi...@intel.com>

(cherry picked from commit b3d7ad85b80bbc404635dca80f5b129f6242bc7a)

Rename the open coded form of this instruction sequence from
rdtsc_ordered() into a generic barrier primitive, barrier_nospec().

One of the mitigations for Spectre variant1 vulnerabilities is to fence
speculative execution after successfully validating a bounds check. I.e.
force the result of a bounds check to resolve in the instruction pipeline
to ensure speculative execution honors that result before potentially
operating on out-of-bounds data.

No functional changes.

Suggested-by: Linus Torvalds <torva...@linux-foundation.org>
Suggested-by: Andi Kleen <a...@linux.intel.com>
Suggested-by: Ingo Molnar <mi...@redhat.com>
Signed-off-by: Dan Williams <dan.j.willi...@intel.com>
Signed-off-by: Thomas Gleixner <t...@linutronix.de>
Cc: linux-a...@vger.kernel.org
Cc: Tom Lendacky <thomas.lenda...@amd.com>
Cc: Kees Cook <keesc...@chromium.org>
Cc: kernel-harden...@lists.openwall.com
Cc: gre...@linuxfoundation.org
Cc: Al Viro <v...@zeniv.linux.org.uk>
Cc: a...@linux.intel.com
Signed-off-by: David Woodhouse <d...@amazon.co.uk>
[jwang: cherry pick to 4.4]
Signed-off-by: Jack Wang <jinpu.w...@profitbricks.com>
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
 arch/x86/include/asm/barrier.h |    4 ++++
 arch/x86/include/asm/msr.h     |    3 +--
 2 files changed, 5 insertions(+), 2 deletions(-)

--- a/arch/x86/include/asm/barrier.h
+++ b/arch/x86/include/asm/barrier.h
@@ -48,6 +48,10 @@ static inline unsigned long array_index_
 /* Override the default implementation from linux/nospec.h. */
 #define array_index_mask_nospec array_index_mask_nospec
+/* Prevent speculative execution past this barrier. */
+#define barrier_nospec() alternative_2("", "mfence", X86_FEATURE_MFENCE_RDTSC, 
+                                          "lfence", X86_FEATURE_LFENCE_RDTSC)
 #define dma_rmb()      rmb()
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -147,8 +147,7 @@ static __always_inline unsigned long lon
         * that some other imaginary CPU is updating continuously with a
         * time stamp.
-       alternative_2("", "mfence", X86_FEATURE_MFENCE_RDTSC,
-                         "lfence", X86_FEATURE_LFENCE_RDTSC);
+       barrier_nospec();
        return rdtsc();

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