2018-02-05 13:24-0600, Janakarajan Natarajan:
> Add the EventSelect and Counter MSRs for AMD Core Perf Extension.
> 
> Signed-off-by: Janakarajan Natarajan <janakarajan.natara...@amd.com>
> ---
>  arch/x86/include/asm/msr-index.h | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/x86/include/asm/msr-index.h 
> b/arch/x86/include/asm/msr-index.h
> index e7b983a..2885363 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -341,7 +341,21 @@
>  
>  /* Fam 15h MSRs */
>  #define MSR_F15H_PERF_CTL            0xc0010200
> +#define MSR_F15H_PERF_CTL0           MSR_F15H_PERF_CTL
> +#define MSR_F15H_PERF_CTL1           (MSR_F15H_PERF_CTL + 2)
> +#define MSR_F15H_PERF_CTL2           (MSR_F15H_PERF_CTL + 4)
> +#define MSR_F15H_PERF_CTL3           (MSR_F15H_PERF_CTL + 6)
> +#define MSR_F15H_PERF_CTL4           (MSR_F15H_PERF_CTL + 8)
> +#define MSR_F15H_PERF_CTL5           (MSR_F15H_PERF_CTL + 10)
> +
>  #define MSR_F15H_PERF_CTR            0xc0010201
> +#define MSR_F15H_PERF_CTR0           MSR_F15H_PERF_CTR
> +#define MSR_F15H_PERF_CTR1           (MSR_F15H_PERF_CTR + 2)
> +#define MSR_F15H_PERF_CTR2           (MSR_F15H_PERF_CTR + 4)
> +#define MSR_F15H_PERF_CTR3           (MSR_F15H_PERF_CTR + 6)
> +#define MSR_F15H_PERF_CTR4           (MSR_F15H_PERF_CTR + 8)
> +#define MSR_F15H_PERF_CTR5           (MSR_F15H_PERF_CTR + 10)
> +

x86 maintainers,

are you ok with this going through the kvm tree?

Thanks.

>  #define MSR_F15H_NB_PERF_CTL         0xc0010240
>  #define MSR_F15H_NB_PERF_CTR         0xc0010241
>  #define MSR_F15H_PTSC                        0xc0010280
> -- 
> 2.7.4
> 

Reply via email to