On Wed, Mar 7, 2018 at 4:47 PM, Jolly Shah <[email protected]> wrote:
> Hi Rob,
>
>
>> -----Original Message-----
>> From: Rob Herring [mailto:[email protected]]
>> Sent: Monday, March 05, 2018 5:46 PM
>> To: Jolly Shah <[email protected]>
>> Cc: [email protected]; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]; Shubhrajyoti Datta <[email protected]>; linux-
>> [email protected]; Jolly Shah <[email protected]>; Rajan Vaja
>> <[email protected]>; [email protected]
>> Subject: Re: [PATCH 2/3] dt-bindings: clock: Add bindings for ZynqMP clock
>> driver
>>
>> On Wed, Feb 28, 2018 at 02:27:40PM -0800, Jolly Shah wrote:
>> > Add documentation to describe Xilinx ZynqMP clock driver bindings.
>> >
>> > Signed-off-by: Jolly Shah <[email protected]>
>> > Signed-off-by: Rajan Vaja <[email protected]>
>> > Signed-off-by: Shubhrajyoti Datta <[email protected]>
>> > ---
>> > +95 dpll_post_src
>> > +96 vpll_int
>> > +97 vpll_pre_src
>> > +98 vpll_half
>> > +99 vpll_int_mux
>> > +100 vpll_post_src
>> > +101 can0_mio
>> > +102 can1_mio
>> > +
>> > +Example:
>> > +
>> > +clk: clk {
>> > + #clock-cells = <1>;
>> > + compatible = "xlnx,zynqmp-clk";
>>
>> How do you control the clocks?
>
> Clocks are controlled by a dedicated platform management controller. Above
> clock ids are used to identify clocks between master and PMU.
What is the interface to the "platform management controller"? Because
you have no registers, I'm guessing a firmware interface? If so, then
just define the firmware node as a clock provider.
Rob
