Quoting David Lechner (2018-03-15 19:52:35) > This adds a new driver for the USB PHY clocks in the CFGCHIP2 syscon > register on TI DA8XX-type SoCs. > > The USB0 (USB 2.0) PHY clock is an interesting case because it calls > clk_enable() in a reentrant way. The USB 2.0 PSC only has to be enabled > temporarily while we are locking the PLL, which takes place during the > clk_enable() callback. > > Signed-off-by: David Lechner <[email protected]> > ---
Applied to clk-next
