On Mon, May 14, 2018 at 12:01:04PM +0100, Suzuki K Poulose wrote: > commit ece1397cbc89c51914fae1aec729539cfd8bd62b upstream > > Some variants of the Arm Cortex-55 cores (r0p0, r0p1, r1p0) suffer > from an erratum 1024718, which causes incorrect updates when DBM/AP > bits in a page table entry is modified without a break-before-make > sequence. The work around is to disable the hardware DBM feature > on the affected cores. The hardware Access Flag management features > is not affected. > > The hardware DBM feature is a non-conflicting capability, i.e, the > kernel could handle cores using the feature and those without having > the features running at the same time. So this work around is detected > at early boot time, rather than delaying it until the CPUs are brought > up into the kernel with MMU turned on. This also avoids other complexities > with late CPUs turning online, with or without the hardware DBM features. > > Cc: sta...@vger.kernel.org # v4.4 > Cc: Catalin Marinas <catalin.mari...@arm.com> > Cc: Mark Rutland <mark.rutl...@arm.com> > Cc: Will Deacon <will.dea...@arm.com> > Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> > --- > Note: The upstream commit is on top of a reworked capability > infrastructure for arm64 heterogeneous systems, which allows > delaying the CPU model checks. This backport is based on the > original version of the patch [0], which checks the affected > CPU models during the early boot. > > [0] https://lkml.kernel.org/r/20180116102323.3470-1-suzuki.poul...@arm.com
Thanks for these, now queued up. greg k-h
