On Tue, 10 Jul 2018 11:40:08 +0000 "Bean Huo (beanhuo)" <bean...@micron.com> wrote:
> Hi, Boris > >> > >> Okay, I think we already had this discussion, but I'm asking it again. > >> What are the possible values for that field and what do they mean? > > > >Still, it's not clear to me what "Internal ECC level" means. It seems that > >NAND > >chips having on-die ECC have this field set to 10b (0x2), 00b seems to be > >reserved for "no on-die ECC", but what are 01b and 11b reserved for? > > > > That position identifies the part as having Internal ECC capability. > The 01b and 11b are reserved for future definition. Bit 7 of READ ID Byte 4 > identifies the > device as an ECC OFF 0x0 or ECC ON 0x1. > > >> Also, is it even used to encode the fact that the NAND has on-die ECC > >> on all your NANDs? We already had the problem of incompatible ID > >> schemes, so I wouldn't be surprised if that was the case here, hence > >> my initial suggestion to base the detection on the model name. > > > >I'd really need to have an answer on that one to take a decision. Also, I > >couldn't find a datasheet for an IT (without E) version of the > >MT29F1G08ABAFAWP part. Does it exist, or can we assume > >MT29F1G08ABAFAWP chips always come with forcibly enabled on-die ECC? > > MT29F1G08ABAFAWP comes in ECC ON only. We didn’t develop a > MT29F1G08ABAFAWP ECC OFF version. Bit 7 of READ ID Byte 4 identifies the > device as an ECC OFF 0x0 or ECC ON 0x1. > Okay. Can you have a look at the patches I sent an let me know if I do the right thing?
