On Sat, Jul 28, 2018 at 2:53 PM, Rik van Riel <[email protected]> wrote: > Clarify exactly what the memory barrier synchronizes with.
Reviewed-by: Andy Lutomirski <[email protected]>
- [PATCH 0/10] x86,tlb,mm: more lazy TLB cleanups & opti... Rik van Riel
- [PATCH 01/10] x86,tlb: clarify memory barrier in swit... Rik van Riel
- Re: [PATCH 01/10] x86,tlb: clarify memory barrier... Andy Lutomirski
- [PATCH 10/10] mm,sched: conditionally skip lazy TLB m... Rik van Riel
- Re: [PATCH 10/10] mm,sched: conditionally skip la... Andy Lutomirski
- Re: [PATCH 10/10] mm,sched: conditionally ski... Rik van Riel
- Re: [PATCH 10/10] mm,sched: conditionally... Andy Lutomirski
- Re: [PATCH 10/10] mm,sched: conditio... Rik van Riel
- [PATCH v2 10/11] x86,tlb: really leave mm on ... Rik van Riel
- [PATCH v2 11/11] mm,sched: conditionally skip... Rik van Riel
- Re: [PATCH v2 11/11] mm,sched: conditiona... Peter Zijlstra
- Re: [PATCH v2 11/11] mm,sched: condi... Rik van Riel
- Re: [PATCH v2 11/11] mm,sched: c... Peter Zijlstra
