On an OLPC XO 1.75 machine, the "security processor" handles the GPIO 71 and 72 interrupts. Don't reset the "route to SP" bit (4).
I'm just assuming the bit 4 is the "route to SP" bit -- it fixes the SP-based keyboard for me and <mach-mmp/regs-icu.h> defines ICU_INT_ROUTE_SP_IRQ to be 1 << 4. When asked for a data sheet, Marvell told me to fuck off, politely. Signed-off-by: Lubomir Rintel <[email protected]> --- drivers/irqchip/irq-mmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-mmp.c b/drivers/irqchip/irq-mmp.c index 25f32e1d7764..1ed38f9f1d0a 100644 --- a/drivers/irqchip/irq-mmp.c +++ b/drivers/irqchip/irq-mmp.c @@ -190,7 +190,7 @@ static const struct mmp_intc_conf mmp_conf = { static const struct mmp_intc_conf mmp2_conf = { .conf_enable = 0x20, .conf_disable = 0x0, - .conf_mask = 0x7f, + .conf_mask = 0x60, }; static void __exception_irq_entry mmp_handle_irq(struct pt_regs *regs) -- 2.17.1
