Hi Tudor, > -----Original Message----- > From: Tudor Ambarus [mailto:[email protected]] > Sent: Thursday, October 11, 2018 9:33 PM > To: Yogesh Narayan Gaur <[email protected]>; linux- > [email protected]; [email protected] > Cc: [email protected]; [email protected]; > [email protected]; [email protected]; > [email protected]; [email protected] > Subject: Re: [PATCH v2 2/2] mtd: spi-nor: add entry for mt35xu512aba flash > > > > On 10/11/2018 11:15 AM, Yogesh Narayan Gaur wrote: > > Add entry for mt35xu512aba Micron NOR flash. > > This flash is having uniform sector erase size of 128KB, have support > > of FSR(flag status register), flash size is 64MB and supports 4-byte > > commands. > > > > Signed-off-by: Yogesh Gaur <[email protected]> > > --- > > Changes for v2: > > - Removed checkpatch warning, 80 character limit. > > > > drivers/mtd/spi-nor/spi-nor.c | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/drivers/mtd/spi-nor/spi-nor.c > > b/drivers/mtd/spi-nor/spi-nor.c index b8b494f..e0d95ac 100644 > > --- a/drivers/mtd/spi-nor/spi-nor.c > > +++ b/drivers/mtd/spi-nor/spi-nor.c > > @@ -1405,6 +1405,10 @@ static const struct flash_info spi_nor_ids[] = { > > { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR > | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, > > { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | > USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, > > > > + /* Micron */ > > + { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512, > > + SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES) }, > > + > > The style is slightly different from what Brian proposed back in > 9648388fc7737365be7a8092e77df78ccc2cd1a4. For consistency reasons, I think > we should use the same style in all entries. >
Ok, I have send the next version of the patches with the style changes as proposed by Brian. -- Regards Yogesh Gaur. > Since I verified the correctness of the patch and my comment targets just a > cosmetic change, I'll let the maintainers decide: > > Reviewed-by: Tudor Ambarus <[email protected]>
