On 10/17/18 1:59 PM, Marcel Ziswiler wrote:
> On Fri, 2018-08-31 at 12:29 +0300, Peter De Schrijver wrote:
>> On Thu, Aug 30, 2018 at 09:42:10PM +0300, Dmitry Osipenko wrote:
>>> Currently all PLL's on Tegra20 use a hardcoded delay despite of
>>> having
>>> a lock-status bit. The lock-status polling was disabled ~7 years
>>> ago
>>> because PLLE was failing to lock and was a suspicion that other
>>> PLLs
>>> might be faulty too. Other PLLs are okay, hence enable the lock-
>>> status
>>> polling for them. This reduces delay of any operation that require
>>> PLL
>>> to lock.
>>>
>>> Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
>>> ---
>>>
>>> Changelog:
>>>
>>> v2: Don't enable polling for PLLE as it known to not being
>>> able to lock.
>>>
>>
>> This isn't correct. The lock bit of PLLE can declare lock too early,
>> but the
>> PLL itself does lock.
>
> Is there an errata documenting this? As I could not really find any
> mentioning of this anywhere at least up to the v11 from Dec 21, 2010 I
> still have access to.
>
> BTW: It looks like also PLLA may not always lock properly with those
> changes. Is there anything known about that as well? Here is what I get
> on various Colibri T20 modules (while random other ones seem to work
> fine):
Could you please try to increase the timeout value?
