The PCIe node is wired to the second PHY of the COMPHY IP.

Suggested-by: Grzegorz Jaszczyk <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
---
 arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts 
b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
index 76a508da80b9..43e8e1edc467 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
@@ -49,6 +49,7 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pcie_pins>;
        reset-gpios = <&gpiosb 3 GPIO_ACTIVE_HIGH>;
+       phys = <&comphy1 0>;
 };
 
 /* J6 */
-- 
2.19.1

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