Add compatible strings for the SiFive E51 family of CPU cores to the RISC-V CPU compatible string documentation. The E51 CPU core is described in:
https://static.dev.sifive.com/FU540-C000-v1.0.pdf Cc: Rob Herring <robh...@kernel.org> Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Albert Ou <a...@eecs.berkeley.edu> Cc: devicet...@vger.kernel.org Cc: linux-ri...@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Paul Walmsley <paul.walms...@sifive.com> Signed-off-by: Paul Walmsley <p...@pwsan.com> --- Documentation/devicetree/bindings/riscv/cpus.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt index adf7b7af5dc3..fb9d4f86f41f 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.txt +++ b/Documentation/devicetree/bindings/riscv/cpus.txt @@ -68,8 +68,9 @@ described below. - compatible: Usage: required Value type: <stringlist> - Definition: must contain "riscv", may contain one of - "sifive,rocket0" + Definition: must contain "riscv", may contain one or + more of "sifive,rocket0", "sifive,e51", + "sifive,e5" - mmu-type: Usage: optional Value type: <string> -- 2.20.0
