On Fri, Dec 14, 2018 at 09:21:50PM -0800, Paul Walmsley wrote: > Add compatible strings for the SiFive E51 family of CPU cores to the > RISC-V CPU compatible string documentation. The E51 CPU core is > described in: > > https://static.dev.sifive.com/FU540-C000-v1.0.pdf > > Cc: Rob Herring <[email protected]> > Cc: Mark Rutland <[email protected]> > Cc: Palmer Dabbelt <[email protected]> > Cc: Albert Ou <[email protected]> > Cc: [email protected] > Cc: [email protected] > Cc: [email protected] > Signed-off-by: Paul Walmsley <[email protected]> > Signed-off-by: Paul Walmsley <[email protected]> > --- > Documentation/devicetree/bindings/riscv/cpus.txt | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt > b/Documentation/devicetree/bindings/riscv/cpus.txt > index adf7b7af5dc3..fb9d4f86f41f 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.txt > +++ b/Documentation/devicetree/bindings/riscv/cpus.txt > @@ -68,8 +68,9 @@ described below. > - compatible: > Usage: required > Value type: <stringlist> > - Definition: must contain "riscv", may contain one of > - "sifive,rocket0" > + Definition: must contain "riscv", may contain one or > + more of "sifive,rocket0", "sifive,e51", > + "sifive,e5"
I can't really tell what are valid combinations from this. It reads that I could list every string here and that would be valid. It is basically 'riscv' plus any other combinations of strings. Rob
