The below patch added this quirk only for the first generation of family 15 processors, over time its noticed that its required for later generations too.
"575203b4747c x86, MCE, AMD: Disable error thresholding bank 4 on some models" This patch extends the quirk to make it applicable till 7th Generation, so as to address the below warning at boot: "[Firmware Bug]: cpu 0, invalid threshold interrupt offset ..." Signed-off-by: Shirish S <[email protected]> --- arch/x86/kernel/cpu/mce/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 672c722..051b536 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1616,7 +1616,7 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) * they're not supported there. */ if (c->x86 == 0x15 && - (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) { + (c->x86_model >= 0x10 && c->x86_model <= 0x7f)) { int i; u64 hwcr; bool need_toggle; -- 2.7.4
