Dt-bindings doc about CPU node of Ingenic XBurst based SOCs.
Signed-off-by: Zhou Yanjie <[email protected]>
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.../devicetree/bindings/mips/ingenic/ingenic,cpu.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
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Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt
diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt
b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt
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+Ingenic Soc CPU
+
+Required properties:
+- device_type: Must be "cpu".
+- compatible: One of:
+ - "ingenic,xburst".
+- reg: The number of the CPU.
+- next-level-cache: If there is a next level cache, point to it.
+
+Example:
+cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "ingenic,xburst";
+ reg = <0>;
+ next-level-cache = <&l2c>;
+};
+
--
2.7.4
