On Thu, 14 Feb 2019, Thomas Gleixner wrote:
> On Thu, 14 Feb 2019, Jan H. Schönherr wrote:
>
> Cc+: Linus (he wrote the original implementation and might have opinions)
>
> > Some systems experience regular interruptions (60 Hz SMI?), that prevent
> > the quick PIT calibration from succeeding: individual interruptions can be
> > so long, that the PIT MSB is observed to decrement by 2 or 3 instead of 1.
> > The existing code cannot recover from this.
> >
> > The system in question is an AMD Ryzen Threadripper 2950X, microcode
> > 0x800820b, on an ASRock Fatal1ty X399 Professional Gaming, BIOS P3.30.
> >
> > Change the code to handle (almost) arbitrary interruptions, as long
> > as they happen only once in a while and they do not take too long.
> > Specifically, also cover an interruption during the very first reads.
> >
> > Signed-off-by: Jan H. Schönherr <j...@schnhrr.de>
> > ---
> >
> > v2:
> > - Dropped the other hacky patch for the time being.
> > - Fixed the early exit check.
> > - Hopefully fixed all inaccurate math in v1.
> > - Extended comments.
>
> That looks halfways sane, but I'm way too tired to wrap my head around
> it right now.
Went through it again and did not find any obvious issue. Nice work!
> Vs. comments: The big comment above pit_verify_msb() needs a big overhaul
> as well.
Would you please fix that up and repost?
Thanks,
tglx
