From: Shahar S Matityahu <shahar.s.matity...@intel.com>

The driver uses msix causes-register to handle both msix and non msix
interrupts when performing sync nmi.  On devices that do not support
msix this register is unmapped and accessing it causes a kernel panic.

Solve this by differentiating the two cases and accessing the proper
causes-register in each case.

Reported-by: Michal Hocko <mho...@kernel.org>
Signed-off-by: Shahar S Matityahu <shahar.s.matity...@intel.com>
Signed-off-by: Luca Coelho <luciano.coe...@intel.com>
---
 .../net/wireless/intel/iwlwifi/pcie/trans.c   | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c 
b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c
index 79c1dc05f948..c4375b868901 100644
--- a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c
+++ b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c
@@ -3644,20 +3644,27 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev 
*pdev,
 
 void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans)
 {
+       struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
        unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT;
+       u32 inta_addr, sw_err_bit;
+
+       if (trans_pcie->msix_enabled) {
+               inta_addr = CSR_MSIX_HW_INT_CAUSES_AD;
+               sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR;
+       } else {
+               inta_addr = CSR_INT;
+               sw_err_bit = CSR_INT_BIT_SW_ERR;
+       }
 
        iwl_disable_interrupts(trans);
        iwl_force_nmi(trans);
        while (time_after(timeout, jiffies)) {
-               u32 inta_hw = iwl_read32(trans,
-                                        CSR_MSIX_HW_INT_CAUSES_AD);
+               u32 inta_hw = iwl_read32(trans, inta_addr);
 
                /* Error detected by uCode */
-               if (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR) {
+               if (inta_hw & sw_err_bit) {
                        /* Clear causes register */
-                       iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD,
-                                   inta_hw &
-                                   MSIX_HW_INT_CAUSES_REG_SW_ERR);
+                       iwl_write32(trans, inta_addr, inta_hw & sw_err_bit);
                        break;
                }
 
-- 
2.20.1

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