On Wed, Apr 24, 2019 at 09:24:31PM +0000, Paul Burton wrote: > Hi Peter, > > On Wed, Apr 24, 2019 at 02:37:00PM +0200, Peter Zijlstra wrote: > > --- a/arch/mips/include/asm/barrier.h > > +++ b/arch/mips/include/asm/barrier.h > > @@ -230,9 +238,6 @@ > > #define nudge_writes() mb() > > #endif > > > > -#define __smp_mb__before_atomic() __smp_mb__before_llsc() > > -#define __smp_mb__after_atomic() smp_llsc_mb() > > - > > /* > > * Some Loongson 3 CPUs have a bug wherein execution of a memory access > > (load, > > * store or pref) in between an ll & sc can cause the sc instruction to > > I think this bit should be part of patch 3, where you currently add a > second definition of these 2 macros.
Whoops, indeed. > Otherwise this one looks reasonable to me. Great, thanks!
