Hi Stephen,
Le jeu. 18 avril 2019 à 23:58, Stephen Boyd <[email protected]> a
écrit :
Quoting Paul Cercueil (2019-04-17 04:24:20)
The pixel clock is directly connected to the output of the PLL, and
not
to the /2 divider.
Cc: [email protected]
Fixes: 226dfa4726eb ("clk: Add Ingenic jz4725b CGU driver")
Signed-off-by: Paul Cercueil <[email protected]>
---
Applied to clk-next
Could you drop this patch?
It turns out it is wrong and the pixel clock is really connected to the
"pll half"
clock. The real bug was elsewhere: the "pll half" clock does not report
the correct
rate. I will send a patch for this one later.
Thanks,
-Paul
