On Sun, May 12, 2019 at 3:25 AM Alex Elder <el...@linaro.org> wrote:
The per-event interrupt handling seems to be more complex than
necessary:
> +/* Enable or disable an event interrupt */
> +static void
> +_gsi_irq_control_event(struct gsi *gsi, u32 evt_ring_id, bool enable)
> +{
> + u32 mask = BIT(evt_ring_id);
> + u32 val;
> +
> + if (enable)
> + gsi->event_enable_bitmap |= mask;
> + else
> + gsi->event_enable_bitmap &= ~mask;
> +
> + val = gsi->event_enable_bitmap;
> + iowrite32(val, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET);
> +}
> +
> +static void gsi_irq_enable_event(struct gsi *gsi, u32 evt_ring_id)
> +{
> + _gsi_irq_control_event(gsi, evt_ring_id, true);
You maintain a bitmap here of the enabled-state, and have
to use a spinlock to ensure that the two are in sync.
> +/* Returns true if the interrupt state (enabled or not) changed */
> +static bool gsi_channel_intr(struct gsi_channel *channel, bool enable)
> +{
> + u32 evt_ring_id = channel->evt_ring_id;
> + struct gsi *gsi = channel->gsi;
> + u32 mask = BIT(evt_ring_id);
> + unsigned long flags;
> + bool different;
> + u32 enabled;
> +
> + spin_lock_irqsave(&gsi->spinlock, flags);
> +
> + enabled = gsi->event_enable_bitmap & mask;
> + different = enable == !enabled;
> +
> + if (different) {
> + if (enabled)
> + gsi_irq_disable_event(channel->gsi, evt_ring_id);
> + else
> + gsi_irq_enable_event(channel->gsi, evt_ring_id);
> + }
> +
> + spin_unlock_irqrestore(&gsi->spinlock, flags);
> +
> + return different;
> +}
This gets called for each active channel, so you repeatedly
have to get the spinlock and read the irq-enabled state for it.
> +static void gsi_isr_ieob(struct gsi *gsi)
> +{
> + u32 evt_mask;
> +
> + evt_mask = ioread32(gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_OFFSET);
> + evt_mask &= ioread32(gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET);
> + iowrite32(evt_mask, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET);
> +
> + while (evt_mask) {
> + u32 evt_ring_id = __ffs(evt_mask);
> +
> + evt_mask ^= BIT(evt_ring_id);
> +
> + gsi_event_handle(gsi, evt_ring_id);
> + }
> +}
However, you start out by clearing all bits here.
Why not skip the clearing and and leave the interrupts enabled,
while moving the GSI_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET
write (for a single channel that was completed) to the end of
gsi_channel_poll()?
Something like
static void gsi_isr_ieob(struct gsi *gsi)
{
u32 evt_mask;
evt_mask = ioread32(gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_OFFSET);
while (evt_mask) {
u32 evt_ring_id = __ffs(evt_mask);
evt_mask ^= BIT(evt_ring_id);
napi_schedule(gsi->evt_ring[evt_ring_id].channel.napi);
}
}
I also removed the GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET
read here, as that is probably more expensive than calling napi_schedule()
for a channel that is already scheduled. Most of the time, I'd expect the
interrupt to only signal a single channel anyway.
Arnd
