Fixes: ba5625c3e27 ("clk: imx: Add clock driver support for imx8mm")
To Frac pll, the gate shift is 13, however to Int PLL the gate shift
is 11.
Cc: <sta...@vger.kernel.org>
Signed-off-by: Peng Fan <peng....@nxp.com>
Reviewed-by: Fabio Estevam <feste...@gmail.com>
Reviewed-by: Jacky Bai <ping....@nxp.com>
---
V2:
Update commit with Fixes, Add R-b and cc stable
drivers/clk/imx/clk-imx8mm.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 1ef8438e3d6d..122a81ab8e48 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -449,12 +449,12 @@ static int __init imx8mm_clocks_init(struct device_node
*ccm_node)
clks[IMX8MM_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out",
"audio_pll2_bypass", base + 0x14, 13);
clks[IMX8MM_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out",
"video_pll1_bypass", base + 0x28, 13);
clks[IMX8MM_DRAM_PLL_OUT] = imx_clk_gate("dram_pll_out",
"dram_pll_bypass", base + 0x50, 13);
- clks[IMX8MM_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out",
"gpu_pll_bypass", base + 0x64, 13);
- clks[IMX8MM_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out",
"vpu_pll_bypass", base + 0x74, 13);
- clks[IMX8MM_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out",
"arm_pll_bypass", base + 0x84, 13);
- clks[IMX8MM_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out",
"sys_pll1_bypass", base + 0x94, 13);
- clks[IMX8MM_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out",
"sys_pll2_bypass", base + 0x104, 13);
- clks[IMX8MM_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out",
"sys_pll3_bypass", base + 0x114, 13);
+ clks[IMX8MM_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out",
"gpu_pll_bypass", base + 0x64, 11);
+ clks[IMX8MM_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out",
"vpu_pll_bypass", base + 0x74, 11);
+ clks[IMX8MM_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out",
"arm_pll_bypass", base + 0x84, 11);
+ clks[IMX8MM_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out",
"sys_pll1_bypass", base + 0x94, 11);
+ clks[IMX8MM_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out",
"sys_pll2_bypass", base + 0x104, 11);
+ clks[IMX8MM_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out",
"sys_pll3_bypass", base + 0x114, 11);
/* SYS PLL fixed output */
clks[IMX8MM_SYS_PLL1_40M] = imx_clk_fixed_factor("sys_pll1_40m",
"sys_pll1_out", 1, 20);
--
2.16.4
