On Fri, May 17, 2019 at 09:10:18AM +0200, Peter Zijlstra wrote: > On Thu, May 16, 2019 at 02:21:46PM +0100, Raphael Gault wrote: > > In order to prevent the userspace processes which are trying to access > > the registers from the pmu registers on a big.LITTLE environment we > > introduce a hook to handle undefined instructions. > > > > The goal here is to prevent the process to be interrupted by a signal > > when the error is caused by the task being scheduled while accessing > > a counter, causing the counter access to be invalid. As we are not able > > to know efficiently the number of counters available physically on both > > pmu in that context we consider that any faulting access to a counter > > which is architecturally correct should not cause a SIGILL signal if > > the permissions are set accordingly. > > The other approach is using rseq for this; with that you can guarantee > it will never issue the instruction on a wrong CPU. > > That said; emulating the thing isn't horrible either.
Yup. Attempting to use rseq is on the todo list. > > + /* > > + * We put 0 in the target register if we > > + * are reading from pmu register. If we are > > + * writing, we do nothing. > > + */ > > Wait _what_ ?!? userspace can _WRITE_ to these registers? Remember that this is in an undefined (trap) handler. If userspace _attempts_ to write to the registers, the CPU will trap to the kernel. The comment is perhaps misleading; when we "do nothing", the common trap handling code will send a SIGILL to userspace. It would probably be better to say something like: /* * If userspace is tries to read a counter that doesn't exist on this * CPU, we emulate it as reading as zero. This happens if userspace is * preempted between reading the idx and actually reading the counter, * and the seqlock and idx have already changed, so it's as-if the * counter has been reprogrammed with a different event. * * We don't permit userspace to write to these registers, and will * inject a SIGILL. */ There is one caveat: userspace can write to PMSELR without trapping, so we will have to context-switch with the task. That only affects indirect addressing of PMU registers, and doesn't have a functional effect on the behaviour of the PMU, so that's benign from the PoV of perf. Thanks, Mark.