Hi Krzysztof, On 7/17/19 10:48 AM, Krzysztof Kozlowski wrote: > On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <[email protected]> wrote: >> >> Add an OPP for FSYS APB which reflects the real possible frequency. >> The bus will have a new parent clock which speed has 600MHz, thus >> a new possible frequency provided by the clock divider is 150MHz. >> According to the documentation max possible frequency for this bus is >> 200MHz. > > Commit msg is good but title could be improved. Focus in the title > what problem/issue you are solving - add intermediate step in scaling > of FSYS APB? The devfreq governor for this bus device follows the set OPP of the master device - WCORE bus and sets the OPP with corresponding ID. Thus, jumping to max frequency 200MHz when the WCORE bus and other devices are operating in the middle of their min-max speed is not needed for FSYS APB and this patch adds the intermediate speed step.
Regards, Lukasz > > Best regards, > Krzysztof > >
