On 30/07/19 10:43, Paolo Bonzini wrote: > On 29/07/19 13:56, Anup Patel wrote: >> The PC register represents program counter whereas the MODE >> register represent VCPU privilege mode (i.e. S/U-mode). >> > Is there any reason to include this pseudo-register instead of allowing > SSTATUS access directly in this patch (and perhaps also SEPC)?
Nevermind, I was confused - the current MODE is indeed not accessible as a "real" CSR in RISC-V. Still, I would prefer all the VS CSRs to be accessible via the get/set reg ioctls. Paolo
