Quoting Andrew Jeffery (2019-07-10 07:10:09) > From: Joel Stanley <[email protected]> > > The clock divisor comes with an enable bit (gate). This was not > implemented as we didn't have access to SD hardware when writing the > driver. Now that we can test it, add the gate as a parent to the > divisor. > > There is no reason to expose the gate separately, so users will enable > it by turning on the ASPEED_CLK_SDIO divisor. > > Signed-off-by: Joel Stanley <[email protected]> > [aj: Minor style cleanup] > Signed-off-by: Andrew Jeffery <[email protected]> > ---
Applied to clk-next
