On Thu, May 21, 2020 at 05:07:16PM +0300, Serge Semin wrote:
> Commit 1aeba347b3a9 ("MIPS: Hardcode cpu_has_mips* where target ISA
> allows") updated the cpu_has_mips* macro to be replaced with a constant
> expression where it's possible. By mistake it wasn't done correctly
> for cpu_has_mips64r1/cpu_has_mips64r2 macro. They are defined to
> be replaced with conditional expression __isa_range_or_flag(), which
> means either ISA revision being within the range or the corresponding
> CPU options flag was set at the probe stage or both being true at the
> same time. But the ISA level value doesn't indicate whether the ISA is
> MIPS32 or MIPS64. Due to this if we select MIPS32r1 - MIPS32r5
> architectures the __isa_range() macro will activate the
> cpu_has_mips64rX flags, which is incorrect. In order to fix the
> problem we make sure the 64bits CPU support is enabled by means of
> checking the flag cpu_has_64bits aside with proper ISA range and specific
> Revision flag being set.
>
> Fixes: 1aeba347b3a9 ("MIPS: Hardcode cpu_has_mips* where target ISA allows")
> Signed-off-by: Serge Semin <[email protected]>
> Cc: Alexey Malahov <[email protected]>
> Cc: Thomas Bogendoerfer <[email protected]>
> Cc: Paul Burton <[email protected]>
> Cc: Ralf Baechle <[email protected]>
> Cc: Arnd Bergmann <[email protected]>
> Cc: Rob Herring <[email protected]>
> Cc: [email protected]
> ---
> arch/mips/include/asm/cpu-features.h | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
applied to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
