On Thu, May 21, 2020 at 05:07:18PM +0300, Serge Semin wrote: > There are bit fields which persist in the MIPS CONFIG and CONFIG6 > registers, but haven't been described in the generic mipsregs.h > header so far. In particular, the generic CONFIG bitfields are > BE - endian mode, BM - burst mode, SB - SimpleBE, OCP interface mode > indicator, UDI - user-defined "CorExtend" instructions, DSP - data > scratch pad RAM present, ISP - instruction scratch pad RAM present, > etc. The core-specific CONFIG6 bitfields are JRCD - jump register > cache prediction disable, R6 - MIPSr6 extensions enable, IFUPerfCtl - > IFU performance control, SPCD - sleep state performance counter, DLSB - > disable load/store bonding. A new exception code reported in the > ExcCode field of the Cause register: 30 - Parity/ECC error exception > happened on either fetch, load or cache refill. Lets add them to the > mipsregs.h header to be used in future platform code, which have them > utilized. > > Signed-off-by: Serge Semin <[email protected]> > Cc: Alexey Malahov <[email protected]> > Cc: Thomas Bogendoerfer <[email protected]> > Cc: Paul Burton <[email protected]> > Cc: Ralf Baechle <[email protected]> > Cc: Arnd Bergmann <[email protected]> > Cc: Rob Herring <[email protected]> > Cc: [email protected] > --- > arch/mips/include/asm/mipsregs.h | 19 +++++++++++++++++++ > arch/mips/kernel/spram.c | 4 ++-- > 2 files changed, 21 insertions(+), 2 deletions(-)
applied to mips-next. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessarily a good idea. [ RFC1925, 2.3 ]
