On Thu, May 21, 2020 at 9:37 PM Kishon Vijay Abraham I <kis...@ti.com> wrote: > > Certain platforms like TI's J721E using Cadence PCIe IP can perform only > 32-bit accesses for reading or writing to Cadence registers. Convert all > read and write accesses to 32-bit in Cadence PCIe driver in preparation > for adding PCIe support in TI's J721E SoC.
Looking more closely I don't think cdns_pcie_ep_assert_intx is okay with this and never can be given the PCI_COMMAND and PCI_STATUS registers are in the same word (IIRC, that's the main reason 32-bit config space accesses are broken). So this isn't going to work at least for EP accesses. And maybe you need a custom .raise_irq() hook to minimize any problems (such as making the RMW atomic at least from the endpoint's perspective). Rob
