Hi Sivaprakash, Sivaprakash Murugesan <[email protected]> wrote on Tue, 9 Jun 2020 16:40:55 +0530:
> SFLASHC_BURST_CFG register is not available on all ipq nand platforms, > it is available only on ipq8064 devices and the nand controller works > without configuring these registers in this platform, so register write > to this can be removed. Maybe it works because the bootloader is setting the register itself. What if you use a different bootloader, or the same bootloader without NAND support? I don't think this is a proper fix, you should instead have a different compatible if the IP is not the same and depending on this compatible do the write, or not. > > Signed-off-by: Sivaprakash Murugesan <[email protected]> > --- > drivers/mtd/nand/raw/qcom_nandc.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/mtd/nand/raw/qcom_nandc.c > b/drivers/mtd/nand/raw/qcom_nandc.c > index 5b11c70..e0afa2c 100644 > --- a/drivers/mtd/nand/raw/qcom_nandc.c > +++ b/drivers/mtd/nand/raw/qcom_nandc.c > @@ -36,7 +36,6 @@ > #define NAND_DEV_CMD1 0xa4 > #define NAND_DEV_CMD2 0xa8 > #define NAND_DEV_CMD_VLD 0xac > -#define SFLASHC_BURST_CFG 0xe0 > #define NAND_ERASED_CW_DETECT_CFG 0xe8 > #define NAND_ERASED_CW_DETECT_STATUS 0xec > #define NAND_EBI2_ECC_BUF_CFG 0xf0 > @@ -2774,7 +2773,6 @@ static int qcom_nandc_setup(struct qcom_nand_controller > *nandc) > u32 nand_ctrl; > > /* kill onenand */ > - nandc_write(nandc, SFLASHC_BURST_CFG, 0); > nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD), > NAND_DEV_CMD_VLD_VAL); > Thanks, Miquèl
