Add the power domain supporting performance state and the corresponding
OPP tables for the sdhc device on sdm845.
Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index db1f82b..67fc87b 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2994,8 +2994,34 @@
<&gcc GCC_SDCC2_APPS_CLK>;
clock-names = "iface", "core";
iommus = <&apps_smmu 0xa0 0xf>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
status = "disabled";
+
+ sdhc2_opp_table: sdhc2-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-9600000 {
+ opp-hz = /bits/ 64 <9600000>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ };
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-201500000 {
+ opp-hz = /bits/ 64 <201500000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
};
qspi: spi@88df000 {
--
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