On 23/07/2020 16:24, Anup Patel wrote: > We add a separate CLINT timer driver for Linux RISC-V M-mode (i.e. > RISC-V NoMMU kernel). > > The CLINT MMIO device provides three things: > 1. 64bit free running counter register > 2. 64bit per-CPU time compare registers > 3. 32bit per-CPU inter-processor interrupt registers > > Unlike other timer devices, CLINT provides IPI registers along with > timer registers. To use CLINT IPI registers, the CLINT timer driver > provides IPI related callbacks to arch/riscv. > > Signed-off-by: Anup Patel <[email protected]> > Tested-by: Emil Renner Berhing <[email protected]> > ---
Acked-by: Daniel Lezcano <[email protected]> -- <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog
