[+cc Andrew, Armen, hpa]
On Thu, Jul 23, 2020 at 02:01:17PM -0400, Alex Deucher wrote:
> On Thu, Jul 23, 2020 at 1:43 PM Logan Gunthorpe <[email protected]> wrote:
> >
> > The AMD Zen 2 root complex (Starship/Matisse) was tested for P2PDMA
> > transactions between root ports and found to work. Therefore add it
> > to the list.
> >
> > Signed-off-by: Logan Gunthorpe <[email protected]>
> > Cc: Bjorn Helgaas <[email protected]>
> > Cc: Christian König <[email protected]>
> > Cc: Huang Rui <[email protected]>
> > Cc: Alex Deucher <[email protected]>
>
> Starting with Zen, all AMD platforms support P2P for reads and writes.
What's the plan for getting out of the cycle of "update this list for
every new chip"? Any new _DSMs planned, for instance?
A continuous trickle of updates like this is not really appealing. So
far we have:
7d5b10fcb81e ("PCI/P2PDMA: Add AMD Zen Raven and Renoir Root Ports to
whitelist")
7b94b53db34f ("PCI/P2PDMA: Add Intel Sky Lake-E Root Ports B, C, D to the
whitelist")
bc123a515cb7 ("PCI/P2PDMA: Add Intel SkyLake-E to the whitelist")
494d63b0d5d0 ("PCI/P2PDMA: Whitelist some Intel host bridges")
0f97da831026 ("PCI/P2PDMA: Allow P2P DMA between any devices under AMD ZEN
Root Complex")
And that's just from the last year, not including this patch.
> > ---
> > drivers/pci/p2pdma.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c
> > index e8e444eeb1cd..3d67a1ee083e 100644
> > --- a/drivers/pci/p2pdma.c
> > +++ b/drivers/pci/p2pdma.c
> > @@ -284,6 +284,8 @@ static const struct pci_p2pdma_whitelist_entry {
> > {PCI_VENDOR_ID_AMD, 0x1450, 0},
> > {PCI_VENDOR_ID_AMD, 0x15d0, 0},
> > {PCI_VENDOR_ID_AMD, 0x1630, 0},
> > + /* AMD ZEN 2 */
> > + {PCI_VENDOR_ID_AMD, 0x1480, 0},
> >
> > /* Intel Xeon E5/Core i7 */
> > {PCI_VENDOR_ID_INTEL, 0x3c00, REQ_SAME_HOST_BRIDGE},
> >
> > base-commit: ba47d845d715a010f7b51f6f89bae32845e6acb7
> > --
> > 2.20.1
> >
