On Fri, Sep 18, 2020 at 06:55:16AM +0000, 劉偉權 wrote: > Hi Serge, > Thanks for your reply. There is a confidential issue that realtek > doesn't offer the detail of a full register layout for configuration > register.
... > > * 0xa4 extension page (0x7) layout. It can be used to disable/enable > > * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. It can > > * also be used to customize the whole configuration register: > > > - * 8:6 = PHY Address, 5:4 = Auto-Negotiation, 3 = Interface Mode Select, > > - * 2 = RX Delay, 1 = TX Delay, 0 = SELRGV (see original PHY datasheet > > - * for details). > > + * 13 = Force Tx RX Delay controlled by bit12 bit11, > > + * 12 = RX Delay, 11 = TX Delay > > Here you've removed the register layout description and replaced itq > with just three bits info. So from now the text above doesn't really > corresponds to what follows. > I might have forgotten something, but AFAIR that register bits > stateq mapped well to what was available on the corresponding > external pins. Hi Willy So it appears bits 3 to 8 have been reverse engineered. Unless you know from your confidential datasheet that these are wrong, please leave the comment alone. If you confidential datasheet says that the usage of bits 0-2 is wrong, then please do correct that part. Andrew